1. Field of the Invention
The field of the invention is data processing, or, more specifically, methods, apparatus, and products for filtering snoop traffic in a multiprocessor computing system.
2. Description of Related Art
When a uniprocessor makes a request for a piece of data, the data is initially supplied by the main memory and along the way it is stored in the cache hierarchy—such as the L2 cache and the L1 cache. Future accesses to the same (or nearby) data can typically be satisfied by the caches.
In multicore and multiprocessor systems that support the shared memory programming model, multiple execution threads may work on the same shared data, and, therefore, multiple caches may hold the same cache line of data. In a shared memory programming model it is possible that the same piece of data (that is data located at a unique location in memory) be simultaneously in use by multiple processors. When there are multiple copies of a block of data in the caches it is imperative that some form of cache coherence is implemented in order to propagate any update to any piece of shared data to all the users of that data. One approach to maintaining cache coherence involves simply invalidating all other replicas of a cache line in the system whenever one processor intends to modify the cache line. This ensures that only one cached copy of the line remains in the system, which may then be safely modified. Later, if other processors in the system want to use that same cacheline again, they are forced to fetch the modified copy, thereby ensuring correctness.
In order to invalidate all other replicas of a cache line in the system whenever one processor intends to modify the cache line, a snoop message may be issued by the processor intends to modify the cache line. The snoop message may be received by all other processors in the system and the cache line that is to be modified may be searched for in the L2 cache and the L1 cache—causing a performance bottleneck as all snoop messages require multiple cache accesses.